An Oxide Failure Reliability Model for Shallow Trench Isolation based LDMOS Devices (1039)

Integrated LDMOS devices in advanced CMOS platforms utilize the Shallow Trench Isolation (STI) as a thicker dielectric separating the field plate gate from the drift layer. In this paper we propose a percolation model that can predict the mean time for failure in the STI for a given protrusion type defect density and depth distribution.