Invited
THE ROLE OF INTERFACES AND DEFECTS IN CONTROLLING THE ELECTRICAL PROPERTIES OF METAL/HIGH-K STACKS ON VARIOUS SEMICONDUCTORS

Future downscaling of metal-oxide-semiconductor (MOS) devices has been challenged in recent years by material-related phenomena such as increased leakage current through the SiO₂ gate oxide and depletion of the poly-Si gate electrode. In order to overcome these challenges, the traditional gate materials have been replaced by high-k dielectrics and by metal electrodes. In parallel with the development of metal gate/high-K/Si MOS transistors, there has been in recent years an increasing emphasis on new channel materials beyond Si, such as Ge and InGaAs, materials that can achieve larger drive currents. The absence of high quality dielectric/InGaAs and dielectric/Ge interfaces due to electrically active defects that either trap carriers or act as centers of fixed charge delays, however, the onset of this application.

The objective of our research is to determine the role of interfaces and defects in controlling the properties of MOS devices consisting of a metal electrode, a high-k dielectric and various semiconducting substrates. The research correlates between material properties (e.g. interface composition, structure and chemical bonding) and electrical properties of the devices. These properties were found to be affected by the dielectrics and metals used and by the annealing temperature and environment before or post metallization.