IMPROVEMENT OF PATTERNING PROCESS BY OPTIMIZATION OF WAFER EDGE EXPOSURE IN LITHOGRAPHY

Scientists and engineers in the field of microelectronics are now able to produce nanometers structures. One of the biggest efforts in microelectronics industry is the motivation to minimize device dimensions while increasing efficiency. The ability to minimize the dimensions strongly depends on the development of patterning technology. The main challenge in this process is to control the uniformity of the critical dimensions (CDs) upon the wafer, mainly due to a different etch profile, resulting in CDs variance between center to edge (CTE), metals shorts, and yield drop.

Here we present a creative and integrative solution to the CTE yield decrease problem by optimizing the exposure energy on wafer edge during lithography process as a compensation for the etching profile.

By reducing the edge exposure energy, the uniformity of the CDs increased as well as the uniformity of the electrical resistance. In addition, the number of short type defects decreased, and the edge yield increased significantly.

Improvement of pattering process was implemented in the product being tested with the approval of the factory manager, in addition, the corresponding factory in Arizona began to run the project to achieve yield improvement as obtained at Intel Kiryat Gat. Following the results achieved in this project, the change was also implemented into the main product family manufactured at the factory.