Micro Machined TSVs for WLP Applications

Micro machined TSV technology allows the technical growth Electronic systems, as SiP or PoP, in 2.5 and 3D allowing and potentiating their complexity. The techniques is already well established, the extension to the different applications at Wafer Level is pertinent and on demanding.
With this project we aim to fabricate 200mm wafers with 725um thick with high TSVs density per area. By using the developed technology, we were able to manufacture 2841 TSVs of 190um diameter on a single silicon wafer. The silicon wafer was patterned and Silicon was drilled using DRIE technology in order to create through Silicon holes with a very stable and uniform aspect ratio all over the wafer area. The silicon was then passivated using SiO2 layer covering both sides of the wafer including the holes walls. This step was performed to assure the electrical isolation between Vias, an essential characteristic for a useful TSV.
The filling of holes with Cu was performed using the electroplating technique which allowed us to build a solid pillar bottom to top free of voids assuring a very good electrical conductivity, essential for the final application in Wafer Level Packaging. To assure the flatness, planarity and uniformity all over the 200mm wafer, a Chemical Mechanical Planarization process was performed allowing future applications as wafer to wafer bonding, redistribution layers etc.