Back-end-of-line CMOS integrated metal-ferroelectric-dielectric-metal FTJ devices for neuromorphic applications

HfO₂-based ferroelectrics have attracted significant interest owing to the material compatibility with CMOS technology, which opens avenues for various device applications. The stable ferroelectric phase at nanometer thickness and the low crystallization temperature (< 500°C for Hf_0.5Zr_0.5O₂) make the materials ideal for integration on top of CMOS metal layers (back-end-of-line). Among different ferroelectric-based devices, ferroelectric tunnel junction (FTJ) memories are well suited for emerging neuromorphic applications due to their low power consumption, non-volatile nature, and potential to attain multiple resistance states through partial switching of domains. As the conventional metal-ferroelectric-metal FTJ stack requires an ultra-thin ferroelectric layer (1-3 nm), it is quite challenging to fabricate with polycrystalline Hf_0.5Zr_0.5O₂ layers. Therefore, in this work we utilize a metal-ferroelectric-dielectric-metal (bilayer) architecture [1], which allows a larger ferroelectric thickness (~10-12 nm) and can still provide a high ON current as the tunneling occurs through the thin dielectric layer (~3 nm). For neuromorphic applications, the FTJ emulating the synaptic function has to be combined with CMOS neuron circuits. To achieve this, we fabricated W-Hf_0.5Zr_0.5O₂-Al₂O₃-W FTJ devices on the back-end-of-line of CMOS chips with neuron circuits. We study the stand-alone FTJ properties by switching I-V and P-V measurements. On the same devices, multiple well-separated resistance states are demonstrated through set and reset pulse modification, which are necessary for neuromorphic applications. As the current density of bilayer FTJs is low (0.1-1pA/µm²), it needs to be amplified to be detected and transmitted across the neuromorphic circuits. We show the amplification of up to 3 times by connecting a FTJ to a NMOS transistor on the chip. Thus, we also demonstrate a hybrid FTJ-CMOS 3D circuit necessary for neuromorphic computing.

[1] V. Deshpande, K. S. Nair, M. Holzer, S. Banerjee, and C. Dubourdieu, Solid State Electronics, 186, pp. 108054 (2021).