C-AND: Mixed writing scheme for disturb reduction in 1T ferroelectric FET memory

Ferroelectricity (FE) in doped HfO₂, which was discovered a decade ago, enabled the integration of FE layers in a standard CMOS process. Ferroelectric field effect transistor (FeFET) memory has shown the potential to meet the requirements of the growing need for fast, dense, low-power, and non-volatile memories (NVM). Yet, current FE-based NVM technologies suffer from several limitations. First. due to possibly asymmetric switching voltages between the polarization states, an unselected cell in an unselected row and unselected column (“diagonal” cell in an array) can be undesirably partially or fully written because the electric field across its ferroelectric layer may be sufficient to write the contrary state, hence cause to undesired write disturbs. Second, like in every NOR-type array, during the read of a selected cell, all the other cells in the same column should not be conductive, otherwise, they may cause read errors due to the summation of leakage currents from unselected devices.

In this work, we propose a memory architecture named crossed AND (C-AND), in which each storage cell consists of a single ferroelectric transistor. The write operation is performed using different write schemes and different absolute voltages, to account for the asymmetric switching voltages of the FeFET. It enables writing an entire wordline in two consecutive cycles and prevents current and power through the channel of the transistor. During the read operation, the current and power are mostly sensed at a single selected device in each column. The read scheme additionally enables reading an entire word without read errors, even along long bitlines. Our Simulations demonstrate that, in comparison to the previously proposed AND architecture, the C-AND architecture diminishes read errors, reduces write disturbs, enables the usage of longer bitlines, and saves up to 2.92X in memory cell area.